Set of integrated capacitor arrangements, especially integrated grid capacitors

ABSTRACT

A set of integrated capacitor arrangements is presented, each of which has a circuitry-effective main capacitor and a connectable correction capacitor. Each capacitor arrangement has an electrically conductive antifuse connection and antifuse interruption between the correction capacitor and the main capacitor, which are produced after the main capacitor has been formed. The connection and interruption enable the capacitance of the capacitor arrangement to be corrected.

This application is the national stage application of internationalapplication number PCT/DE2003/01956, filed on Jun. 12, 2003, whichclaims the benefit of priority to German Patent Application DE10230697.4, filed on Jul. 8, 2002, incorporated herein by reference.

The invention relates to an integrated capacitor arrangement containingat least one circuitry-effective main capacitor.

From an integrated arrangement, individual components cannot bemechanically separated from one another without destroying thecomponents. Layer application methods and layer patterning methods,inter alia, are used as fabrication techniques for integratedarrangements.

A capacitor contains two electrodes opposite one another between which adielectric is arranged. Examples of integrated capacitors are:

-   -   so-called MIM capacitors (Metal Insulator Metal),    -   stacked capacitors, also referred to as sandwich capacitors, or    -   grid capacitors.

A capacitance is circuitry-effective if it is not only parasitic, i.e.actually undesired, but is also necessary for the functioning of thecircuit arrangement. By way of example, circuitry-effective capacitorsserve as:

-   -   blocking or backup capacitor,    -   part of a resonant circuit,    -   charging capacitor, or    -   for storing digital information.

In the fabrication of so-called BEOL capacitances (Back End of Line) orof a far BEOL capacitance in integrated form, considerable variationsarise in the capacitance values. The variation results from geometrydeviations on account of process inhomogeneities. The variations occurwithin a semiconductor wafer, within a production batch and also betweendifferent production batches. If the capacitance value of a capacitorlies outside the predetermined specification limits, then the result isa so-called loss of performance or even a loss of yield of thecorresponding integrated circuit.

It is an object of the invention to specify a simple-to-fabricate set ofcapacitor arrangements whose capacitance is as near as possible to apredetermined desired capacitance. In particular, the intention is tospecify a set of grid capacitors.

The set according to the invention contains at least two integratedcapacitor arrangements, which have been produced in accordance withidentical geometrical designs or layouts and which each contain acircuitry-effective main capacitor and at least one correctioncapacitor. One capacitor arrangement contains an electrically conductiveconnection between the correction capacitor and the main capacitor, theconnection having been produced after the production of the maincapacitor of this capacitor arrangement. The other capacitor arrangementcontains an electrically insulating interruption between the samecorrection capacitor and the main capacitor, the interruption havingbeen produced in accordance with the geometrical designs.

If corrections have to be carried out, for example, only in the case of20% of the capacitor arrangements fabricated, in order to achieve thedesired capacitance, then the outlay decreases considerably comparedwith a correction possibility in which the correction can be performedonly by disconnection of capacitors. This is because, in the case ofsuch a correction, capacitors would need to be locally disconnected in80% of the capacitor arrangements.

In one development, the connection is produced in a simple manner bylocal heating, so that components in proximity to the connection areprotected from an increased thermal loading. Moreover, permanent linkscan be produced by local heating in a simple manner. Compared with theproduction of interruptions by local heating, links can be implementedby local heating at lower temperatures. The thermal loading is thus low,particularly during the production of a multiplicity of links on asemiconductor wafer.

The local heating is carried out for example with the aid of a laserbeam. This affords a possibility of increasing or decreasing thecapacitance of the circuitry-effective main capacitor through connectionin parallel or in series with the correction capacitors. This correctionpossibility allows integrated capacitor arrangements with predeterminedcapacitance values to be produced in a simple manner.

In one development, the connection contains two interconnect sectionswhich are spaced apart from one another and between which only adielectric is arranged. The materials of the interconnect sections andof the dielectric are chosen such that material warpages of theinterconnect which penetrate through the dielectric arise during theheating. By way of example, it is possible here to utilize the otherwiseundesirable “spiking” for producing an electrical connection. In analternative configuration, the dielectric contains doping atoms whichchange the conductivity of the dielectric during the heating. Activationof the doping atoms is an expression that is also used in this context.However, there are also other possibilities for producing theconnection, which is also referred to as an antifuse.

In a next development, the circuit arrangements contain at least onefurther correction capacitor, which is disconnected from the maincapacitor or has been connected to the main capacitor.

The development is based on the consideration that the capacitancevalues of integrated capacitors that are actually to be constructedidentically vary around a desired value both downward and upward.Corrections can be restricted to a minimum if it is both possible tocorrect the capacitance value toward larger capacitance values andpossible to correct it toward smaller capacitance values. The furthercorrection capacitor affords this second correction possibility incomparison with the abovementioned correction capacitor with thecapacitors connected in parallel.

In one development, a further interruption for disconnecting the furthercorrection capacitor is produced by local heating. The local heating canbe carried out, for example, with the aid of a laser beam or with theaid of a current surge through an interconnect constriction.

In another development, dielectrics of the capacitors are formed by adielectric between metallization layers in which connection sections ofconnections to integrated semiconductor components of the integratedcapacitor arrangement are situated. It is possible to use a differentdielectric in the region of the capacitor than in the remaining regionbetween the metallization layers, e.g. a dielectric having a higherdielectric constant. Examples of such capacitors are stacked capacitorsor grid capacitors. In other words, the electrodes of a capacitor lie inmore than two metallization layers. In the case of such capacitors, inone configuration, not only electrodes in the topmost metallizationlayer but also electrodes in lower metallization layers are disconnectedin terms of circuitry or added in terms of circuitry during thecorrection. The linking elements and interruptions for the lowerelectrodes are situated either in the lower metallization layer, so thatit is necessary, for example, to provide cutouts of corresponding depthfor a laser beam, or in an upper metallization layer, to whichconnections from the lower metallization layer lead.

In another development, dielectrics of the capacitors have a thicknesswhich is significantly less than the thickness of the dielectric betweenmetallization layers. Examples of such capacitors are MIM capacitors. Inother words, at least one electrode of the capacitor lies outside ametallization layer.

In a next development, the capacitance of a correction capacitor amountsto less than ⅓, less than 1/10, less than 1/100 or less than 1/1000 ofthe capacitance of a main capacitor. This measure means that finetrimming is possible. Thus, with possibilities for correction in thethousandths range, the capacitance values of two capacitor arrangementsof the same integrated circuit arrangement can be coordinated with oneanother very precisely. This is absolutely necessary for someapplications.

The invention additionally relates to a set of grid capacitors withcorrection transverse electrodes. Individual transverse electrodes ofthe grid capacitors also afford a possibility for correction of thecapacitance during the production. The abovementioned technical effectstherefore apply particularly to the grid capacitors.

Exemplary embodiments of the invention are explained below withreference to the accompanying drawings, in which:

FIG. 1 shows a plan view of an MIM capacitor arrangement,

FIG. 2 shows a plan view of a grid capacitor arrangement,

FIG. 3 shows a transverse electrode of a grid capacitor with twointerruption possibilities,

FIG. 4 shows a transverse electrode of a grid capacitor with acontinuous interruption possibility, and

FIG. 5 shows method steps for correcting the capacitance of anintegrated capacitor.

FIG. 1 shows a plan view of an MIM capacitor arrangement 10, whichcontains a main capacitor 12 connected to an electronic circuit and aplurality of disconnectable capacitors situated to the right of the maincapacitor 12, of which only one disconnectable capacitor 14 isillustrated. The dielectric is not illustrated in FIG. 1 for reasons ofimproved clarity.

In the capacitor arrangement 10, a plurality of connectable capacitorsare situated to the left of the main capacitor 12, of which oneconnectable capacitor 16 is illustrated in FIG. 1. The capacitors 12 to16 are constructed identically except for their longitudinal dimensions.The capacitors 12, 14 and 16 respectively contain a bottom electrode 18,20 and 22 near the substrate and an electrode 24, 26 and 28 remote fromthe substrate. The bottom electrodes 18, 20 and 22 are longer than therespectively associated electrode 24, 26 and 28 remote from thesubstrate and project beyond the electrode 24, 26 and 28 remote from thesubstrate in the longitudinal direction on both sides, so that terminalregions for vertically running contacts 30 are produced at the bottomelectrodes 18, 20 and 22 near the substrate.

The main capacitor 12 and the disconnectable capacitors 14 areelectrically connected in parallel by interconnects 32 between thebottom electrodes 18, 20 and by interconnects 34 between the electrodes24, 26 remote from the substrate. As seen geometrically, however, thedisconnectable capacitors 14 are arranged in a row one behind the other.The interconnects 32 and 34 are situated in an upper metallizationlayer. A cutout 36 and 38 in an insulating material (not illustrated)which covers the interconnects 32 and 34 respectively leads to eachinterconnect 32 and 34. Through the cutouts 36 and 38, during acorrection of the capacitance of the main capacitor 12, regions 40 and42 of an interconnect 32 and 34, respectively, can be vaporized with theaid of a laser beam, thereby producing an interruption.

On the other hand, the connectable capacitors 16 can be electricallyconnected in parallel with the main capacitor 12 with the aid ofinterconnects 52 between the bottom electrodes 18, 22 and interconnects54 between the electrodes 24, 28 remote from the substrate.Geometrically, however, the connectable capacitors 16 are arranged in arow. The interconnects 52 and 54 are also situated in an uppermetallization layer.

Cutouts 56 and 58 lead through an insulating material (not illustrated)as far as linking regions 60 and 62 of the interconnects 52 and 54,respectively. The linking regions 60, 62 form so-called antifuses, i.e.a connection possibility which forms a permanent electrically conductiveconnection between the sections of the interconnect 52 and aninterconnect 54, respectively, upon the impingement of a laser beam.

The main capacitor 12 has a length La in the longitudinal direction ofthe capacitor arrangement 10, said length being greater than lengths Lbof the disconnectable capacitors 14 and lengths Lc of the connectablecapacitors 16. As a result, a capacitance C(0) of the main capacitor 12is also greater than a capacitance Cm(I) of the capacitor 14. In thiscase I is a natural number for designating the last disconnectablecapacitor 14. The disconnectable capacitors not illustrated havecapacitances Cm(1) to Cm(I-1) which are equal to the capacitance Cm(I)in the exemplary embodiment explained.

The capacitance C(0) of the main capacitor 12 is likewise greater thanthe capacitance Cp(1) of the connectable capacitor 16. The connectablecapacitors not illustrated in FIG. 1 have capacitances Cp(2) to Cp(N),which are equal to the capacitance Cp(1) or Cm(I). In this case, N is anatural number for designating the last connectable capacitor.

The correction of the capacitance of the capacitor arrangement 10 isexplained in more detail below with reference to FIG. 5.

In another exemplary embodiment, there is only one disconnectablecapacitor 14 and one connectable capacitor 16 to the right and left,respectively, of the main capacitor 12. In a next exemplary embodimentthere is only one or a plurality of connectable capacitors 16 and,respectively, only one or a plurality of disconnectable capacitors 14beside the main capacitor 12. In a next exemplary embodiment thecapacitances Cm(1) to Cm(I) of the capacitor arrangement 10 aredifferent from one another. The capacitances Cp(1) to Cp(N) of thecapacitor arrangement 10 can also be made different from one another.

FIG. 2 shows a plan view of a grid capacitor arrangement 110, whichcontains a main capacitor 112 connected to a circuit and a plurality ofdisconnectable capacitors, one capacitor 114 of which is illustrated inFIG. 2. Furthermore, the grid capacitor arrangement 110 contains aplurality of connectable capacitors, one capacitor 116 of which isillustrated in FIG. 2. Only the upper electrode of the main capacitor112 and of the capacitor 114 and of the capacitor 116 is respectivelyillustrated in FIG. 2. In the underlying metallization layers there arefurther electrodes having the same profile as the upper electrodes. In afirst exemplary embodiment, the electrodes of a capacitor 112, 114 and116 which are situated in the different metallization layers areconnected among one another in each case by at least one verticalcontact. Interconnects between capacitors 112, 114 and 116 are situatedonly in the upper metallization layer.

In the upper metallization layer, the main capacitor 112 contains twocomb-shaped electrodes whose tines mesh with one another. By way ofexample, four transverse electrodes 120 to 126 lined up in a uniformgrid dimension branch off from a longitudinal electrode 118. On alongitudinal electrode 128 opposite the longitudinal electrode 118,there are arranged, transversely with respect to the longitudinalelectrode 128, exactly as many transverse electrodes 130 to 136 as onthe longitudinal electrode 118, i.e. four transverse electrodes 130 to136 which extend into the interspaces between the transverse electrodes120 to 126. A meandering interspace is thus formed between thetransverse electrodes 120 to 126 and 130 to 136, said interspace beingfilled by a dielectric. The length of the meander of the main capacitor112 shall again be La.

The disconnectable capacitors and the connectable capacitors areconstructed like the main capacitor 112, but contain shorterlongitudinal electrodes 140, 142, 144 and 146, respectively from each ofwhich, by way of example, only two transverse electrodes 150 to 160branch.

Situated between the longitudinal electrode 118 and the longitudinalelectrode 142 of the capacitor 114 is a region 162, to which a cutout164 leads from the surface of the integrated circuit. Situated betweenthe longitudinal electrode 128 and the longitudinal electrode 140 of thecapacitor 114 is a region 166, to which a further cutout 168 leads.Through the cutouts 164 and 168, it is possible, with the aid of a laserbeam, to produce an interruption between the longitudinal electrodes 118and 142 and the longitudinal electrodes 128 and 140 in the region 162and 166, respectively. As a result, all the disconnectable capacitors114 can be disconnected from the main capacitor 112. Situated betweenthe further disconnectable capacitors are further regions 170 and 172,to which cutouts 174 and 176 lead, so that disconnection can also beeffected at other locations.

A linking region 180 is situated between the longitudinal electrode 118and the longitudinal electrode 146 of the correction capacitor 116. Alinking region 182 is situated between the longitudinal electrode 128and the longitudinal electrode 144 of the capacitor 116. A cutout 184and 186 leads to the linking region 140 and to the linking region 182,respectively. Through the cutouts 184 and 186, the linking regions 180and 182 can be locally heated with the aid of a laser beam. During thelocal heating, a connection is produced between the longitudinalelectrode 118 and the longitudinal electrode 146, and between thelongitudinal electrode 128 and the longitudinal electrode 144.Electrically conductive connections to further connectable capacitors116 can be produced with the aid of further linking regions 190, 192 towhich cutouts 194 and 196, respectively, lead.

The meander of the main capacitor 112 has a length La, which is greaterthan a length Lb of a meander of the disconnectable capacitor 114 and alength Lc of a meander of the connectable capacitor 116. As a result, acapacitance C(0) of the main capacitor 112 is greater than a capacitanceCm(I) of the disconnectable capacitor 114. Further capacitances Cm(1) toCm(I-1) of further disconnectable capacitors are equal to thecapacitance Cm(I). A capacitance Cp(1) of the connectable capacitor 116is equal to the capacitance Cm(1). Capacitances Cp(2) to Cp(N) of thefurther disconnectable capacitors 116 are equal to the capacitanceCp(1).

The correction of the capacitance of the circuit arrangement 110 isexplained in more detail below with reference to FIG. 5.

In another exemplary embodiment, there are cutouts which lead intodifferent metallization layers, for example to connection orinterruption possibilities which are arranged offset with respect toconnection or interruption possibilities situated above or below thelatter. In an alternative exemplary embodiment, linking regions orregions for interruptions are arranged in an upper metallization layereven though they also relate to electrodes in lower metallizationlayers. Furthermore, the capacitances Cm(1) to Cm(I) or Cp(1) to Cp(N)of the capacitor arrangement 110 may have capacitances that differ fromone another.

FIG. 3 shows a transverse electrode 200 of a grid capacitor. Thetransverse electrode 200 has a region 202 over approximately one thirdof its length and a region 204 over approximately two thirds of itslength. A cutout 206 leads to the region 202. A cutout 208 leads to theregion 204. During the correction of the capacitance of the gridcapacitor to which the transverse electrode 200 belongs, either aninterruption is produced in the region 202 or an interruption isproduced in the region 204. If the interruption is produced in theregion 202, then only approximately one third of the transverseelectrode 200 is circuitry-effective. By contrast, if an interruption isproduced in the region 204, then approximately two thirds of thetransverse electrode 200 are circuitry-effective. Through the selectionof a region 202 or 204, it is possible to implement corrections of thecapacitance of the grid capacitor in the thousandths range.

The length of the transverse electrode 200 is 10 micrometers, forexample. The width is 0.5 micrometer, for example, so that a process ofsevering using a laser beam is possible without any difficulty.

FIG. 4 shows a transverse electrode 220, to which a cutout 222 leads.The cutout 222 extends approximately over the entire length of thetransverse electrode 220. As a result, it is possible to interrupt thetransverse electrode 220 at any desired location. In other words, theinterruption points can be placed continuously along the longitudinalaxis of the transverse electrode 220.

In other exemplary embodiments of transverse electrodes 200 and 220,linking regions are used instead of, or in combination with, the regionsserving for interruption. The interruption regions and/or the linkingregions are arranged either on one transverse electrode of a gridcapacitor or on a plurality of transverse electrodes of the gridcapacitor.

FIG. 5 shows method steps for correcting the capacitance of anintegrated capacitor arrangement, e.g. according to FIGS. 1, 2, 3 or 4.In the front end of the method, in a design and simulation stage, thevariation of the capacitance of the integrated circuit arrangementaround a desired capacitance is determined, for example empirically oron the basis of simulation runs, see method step 300. Correctionpossibilities are provided depending on the capacitance variations, seemethod step 302. The correction possibilities are, for example,disconnectable capacitors, connectable capacitors, disconnectablecapacitor regions and/or connectable capacitor regions. The correctionpossibilities are prescribed in method step 302 taking account of theexpected capacitance variation such that, with regard to the overallproduction, the fewest possible interruptions and links have to beproduced by heating using the laser beam.

The actual correction method begins in a method step 304, which isfollowed by the processing of a wafer, see method step 306. By way ofexample, transistors are produced in a semiconductor material of thewafer. Afterward, metallization layers are applied, capacitors alsobeing produced.

In a method step 308, a measurement is used to detect the actualcapacitance of an integrated capacitor arrangement, i.e. in particularthe capacitance of the main capacitor 12, 112 together with thecapacitances of the disconnectable capacitors 14, 114.

In a subsequent method step 310, the actual capacitance is compared withthe desired capacitance. If the actual capacitance is less than orgreater than the desired capacitance, in particular less than or greaterthan a predetermined tolerance range, then method step 310 is directlyfollowed by a method step 312. In method step 312, a check is made todetermine whether the actual capacitance is greater than the desiredcapacitance. If this is the case, then method step 312 is followed by amethod step 314, in which interruptions are produced in the integratedcapacitor arrangement with the aid of a laser beam, disconnectablecapacitors 14, 114 being disconnected from the main capacitor 12, 112.The capacitance of the capacitor arrangement decreases. A disconnectionof an electrode section from a transverse electrode is also carried outas an alternative.

By contrast, if it is ascertained in method step 312 that the actualcapacitance is less than the desired capacitance, then method step 312is directly followed by a method step 316. In method step 316, linkingregions are heated with the aid of a laser beam. As a result,connectable capacitors 16, 116 are supplementarily connected to the maincapacitor 12, 112 or to a main region. The capacitance of the capacitorarrangement thus increases in the direction of the desired capacitance.A connection of electrode sections of a transverse electrode is alsocarried out as an alternative.

By contrast, if it is ascertained in method step 310 that actualcapacitance and desired capacitance match, then a method step 318follows directly afterward. Method step 318 is also executed aftermethod step 314 or method step 316. The wafer is processed further inmethod step 318. In this case, inter alia, a passivation layer isapplied, which closes off the cutouts for the laser beam.

In a further method step 320, the circuits arranged on the wafer aresingulated and encapsulated in housings. The method is ended in a methodstep 322.

In another exemplary embodiment, the correction is carried out after thesingulation of the circuits. By way of example, current surges are usedto heat the interruption regions or the linking regions. Theinterrogations in method steps 310 and 312 can also be formulateddifferently.

The method specified affords the following advantages:

-   -   the variations in the capacitances caused by geometry or process        fluctuations can subsequently be corrected in a simple manner.        The yield or the performance can thus be increased.    -   The possibility of subsequent correction furthermore allows        individual capacitance matching for the respective integrated        circuit. Capacitance matching specifically coordinated with        other circuit elements can thus be performed, e.g. for the        purpose of optimum setting of an operating point. This is        advantageous, particularly when the other circuit elements can        no longer be corrected.

By disconnecting or adding regions of the capacitor with the aid ofso-called fuses or antifuses, it is thus possible to subsequentlycorrect the influence of process and geometry fluctuations on theparameters of the main capacitor, in particular on the capacitance andon the resistance (and thus on the RC constant).

During the correction in method steps 310 to 316, it is possible to usethe following formula:Ccorr=C(0)−sum(i=1 to I 1 over Cm(i))+sum(n=1 to N 1 over Cp(n)),where the quantities used have already been explained above, except forthe quantities I1 and N1. The index i in the summation over thecapacitances Cm must take account of all the disconnected capacitors,where I1 designates the last disconnected capacitor. The index in thesummation over the capacitances Cp must take account of all theconnected capacitances, where N1 designates the last connectedcapacitor. Furthermore, it must be taken into consideration that eithercapacitors are connected or disconnected.

If the capacitances Cm and Cp are identical, then it is possible,instead of the sum, to effect multiplication by a factor specifying thenumber of disconnected capacitors or connected capacitors.

In the determination of the capacitance variation, it is possible to usethe following relationships applicable to a plate capacitor:C=ε0·εr·Aeff/Deff,where ε0, εr represent the corresponding dielectric constants, Aeffrepresents the effective electrode area and Deff represents theeffective distance between electrodes. A fluctuation in the area ΔAeffor in the distance ΔDeff then causes a change in the capacitance of:ΔC=ΔAeff/Aeff or ΔC=ΔDeff/Deff

To a first approximation, the effective electrode area corresponds, inthe case of:

a) the MIM capacitors: to the overlapping area of the electrodes,

b) the sandwich capacitors: to the area of the metal electrodes,

c) the grid capacitors: to the side area of the interconnects, whichresults from the length L and the thickness T.

The effective distance between electrodes corresponds, in the case of:

a) the MIM capacitors: to the thickness of the dielectric, which differsfrom the dielectric between the metallization layers,

b) the sandwich capacitors: to the thickness of the intermetaldielectric,

c) the grid capacitors: to the thickness of the intrametal dielectric,i.e. the so-called spacing.

In grid capacitors, for example, another influencing factor is theformation of corners. These influencing quantities can at least bedetected by measurement and then be taken into account.

The fluctuations in the capacitances may have the followingprocess-dictated causes:

a) MIM capacitors: fluctuations in the thickness of the MIM dielectric,e.g. due to inhomogeneous deposition rates over the wafer, or differentroughness of the lower electrode.

b) Sandwich capacitors: fluctuations in the thickness of the intermetaldielectric, e.g. thickness fluctuations due to polishing inhomogeneitiesor fluctuations in the etching depth over the wafer.

c) Grid capacitors: fluctuations in the distance between electrodes dueto variation of the thickness of the intrametal dielectric caused e.g.by lithography fluctuations, RIE patterning (Reactive Ion Etching) withthe use of aluminum or by trench etching with the use of copper. Furthercauses are fluctuations in the electrode area due to variation of theinterconnect thickness or due to CMP fluctuations (Chemical MechanicalPolishing), so-called dishing, non-right-angled trench profile with theuse of copper or due to inhomogeneous deposition rates.

In MIM capacitors and sandwich capacitors, the capacitance is correctedby direct disconnection or connection of M area segments of theelectrode:A=A 0±sum(i=1 to M over Ai),where A0 is the electrode basic area that can no longer be corrected, Mis a natural number and Ai is the disconnectable or connectable discretearea elements. The minus sign applies to the disconnectable areaelements. The plus sign applies to the connectable area elements.

In the grid capacitors, the electrode area A is set by way of the lengthL of the interconnect: A=L·T, where T is the mean interconnect thicknesswithin the capacitor structure. Through disconnection or connection of Minterconnect segments, e.g. n discrete segments Li of the electrode,correction is effected as follows:L=L 0±sum(i=1 to M over Li)where L0 denotes the electrode basic length that can no longer becorrected, M denotes a natural number and Li denotes the disconnectableor connectable discrete interconnect segments. The minus sign applies tothe disconnectable interconnect segments. The plus sign applies to theconnectable interconnect segments.

LIST OF REFERENCE SYMBOLS

-   10 MIM capacitor arrangement-   12 Main capacitor-   14 Disconnectable capacitor-   16 Connectable capacitor-   18, 20, 22 Bottom electrode near the substrate-   24, 26, 28 Electrode remote from the substrate-   30 Contact-   32, 34 Interconnect-   36, 38 Cutout-   40, 42 Region-   52, 54 Interconnect-   56, 58 Cutout-   60, 62 Linking region-   La to Lc Length-   C(0), Cm(1), Cp(1) Capacitance-   110 Grid capacitor arrangement-   112 Main capacitor-   114 Disconnectable capacitor-   116 Connectable capacitor-   118 Longitudinal electrode-   120 to 126 Transverse electrode-   128 Longitudinal electrode-   130 to 136 Transverse electrode-   140 to 146 Longitudinal electrode-   150 to 160 Transverse electrode-   162 Region-   164 Cutout-   166 Region-   168 Cutout-   170, 172 Region-   174, 176 Cutout-   180, 182 Linking region-   184, 186 Cutout-   190, 192 Linking region-   194, 196 Cutout-   200 Transverse electrode-   202, 204 Region-   206, 208 Cutout-   220 Transverse electrode-   222 Cutout-   300 Determination of the capacitance variation-   302 Provide correction possibility-   304 Start-   306 Wafer processing-   308 Detection of the actual capacitance-   310 Actual equal to desired?-   312 Actual>desired?-   314 Interruption-   316 Linking-   318 Passivation-   320 Singulation-   322 End

1. A set of integrated capacitor arrangements, having at least twointegrated capacitor arrangements, which have been produced inaccordance with identical geometrical designs and which each contain acircuitry-effective main capacitor and at least one correctioncapacitor, having an electrically conductive antifuse connection betweenthe correction capacitor and the main capacitor in a first of thecapacitor arrangements, the connection having been produced after theproduction of the main capacitor of the first capacitor arrangement,having an electrically insulating antifuse interruption between thecorrection capacitor of the first capacitor arrangement and the maincapacitor in a second of the capacitor arrangements, the interruptionhaving been produced in accordance with the geometrical designs, havingat least one further correction capacitor in each capacitor arrangement,having a further electrically conductive fuse connection between thefurther correction capacitor and the main capacitor in the firstcapacitor arrangement, the further connection having been produced inaccordance with the geometrical designs, and having a furtherelectrically insulating fuse interruption between the further correctioncapacitor in the first capacitor arrangement and the main capacitor inthe second capacitor arrangement, the interruption having been producedafter production of the main capacitor of the second capacitorarrangement.
 2. The capacitor arrangements as claimed in claim 1,wherein the connection and the interruption are situated at identicalpositions in the capacitor arrangements.
 3. The capacitor arrangementsas claimed in claim 1, wherein at least one of: the connection has beenproduced by local heating and the connection contains a material warpagewhich penetrates through a dielectric.
 4. The capacitor arrangements asclaimed in claim 1, wherein at least one of: a material covering theconnection contains a cutout leading to the connection, a materialcovering the interruption contains a cutout leading to the interruption,and the cutouts are filled with a passivating material.
 5. The capacitorarrangements as claimed in claim 1, wherein the further interruptionarose as a result of local heating and vaporization of an electricallyconducting section.
 6. The capacitor arrangements as claimed in claim 1,wherein dielectrics of the capacitors have a thickness which is equal toa thickness of a dielectric between metallization layers in whichconnection sections of connections to integrated semiconductorcomponents are situated.
 7. The capacitor arrangements as claimed inclaim 1, wherein at least one of: the capacitors have electrodessituated in more than two metallization layers, and the electrodes areformed in a whole-area or grid-like manner.
 8. The capacitorarrangements as claimed in claim 1, wherein dielectrics of thecapacitors have a thickness which is less than a thickness of adielectric between metallization layers in which connection sections ofconnections to integrated semiconductor components are situated.
 9. Thecapacitor arrangements as claimed in claim 1, wherein a capacitance ofone of the correction capacitors amounts to less than ⅓ of a capacitanceof the main capacitor to which the correction capacitor is connected.10. A method for producing a set of integrated grid capacitors, themethod comprising: forming at least two integrated grid capacitors inaccordance with identical geometrical designs, each grid capacitorcontaining a plurality of transverse electrodes forming acircuitry-effective main part of the grid capacitor, forming at leasttwo correction transverse electrodes arranged at identical positions inthe grid capacitors to have circuitry-effective lengths of differentmagnitudes after the production of the main part, thecircuitry-effective length of each correction transverse electrode thathas been changed having been lengthened by production of an electricallyconductive connection or having been shortened by at least one of anelectrically insulating interruption and by vaporization of part of thecorrection transverse electrode, and, in a material covering theshortened correction transverse electrode, forming at least one cutoutleading at least one of: to the shortened correction transverseelectrode and to a region at which the shortened correction transverseelectrode was arranged prior to the vaporization.
 11. The method asclaimed in claim 10, wherein the cutout is filled with a passivatingmaterial.
 12. The method as claimed in claim 11, wherein a plurality ofcutouts lead to a correction transverse electrode, or wherein one cutoutwhich essentially covers the entire region of the original correctiontransverse electrode leads to a correction transverse electrode.